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| STS3DPF60L DUAL P-CHANNEL 60V - 0.10 - 3A SO-8 STripFETTM MOSFET Table 1: General Features TYPE STS3DPF60L s s Figure 1: Package RDS(on) < 0.12 ID 3A VDSS 60 V s TYPICAL RDS(on) = 0.10 @ 10V STANDARD OUTLINE FOR EASY AUTOMATED SURFACE MOUNT ASSEMBLYY LOW THRESHOLD DRIVE SO-8 DESCRIPTION This MOSFET is the latest development of STMicroelectronis unique "Single Feature SizeTM" stripbased process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. Figure 2: Internal Schematic Diagram APPLICATIONS s DC-DC CONVERTERS Table 2: Order Codes PART NUMBER STS3DPF60L MARKING S3DPF60L PACKAGE SO-8 PACKAGING TAPE & REEL Rev. 1 September 2004 1/9 STS3DPF60L Table 3: Absolute Maximum ratings Symbol VDS VDGR VGS ID IDM(*) Ptot Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Storage Temperature Operating Junction Temperature Value 60 60 16 3 1.9 12 2 -55 to 150 Unit V V V A A A W C (*) Pulse width limited by safe operating area. Table 4: Thermal Data Rthj-amb (*) (*)Thermal Resistance Junction-ambient 62.5 C/W When Mounted on 1 inch2 FR-4 board, 2 oz of Cu t 10 s ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) Table 5: On/Off Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating ,TC= 125C VGS = 16 V VDS = VGS, ID = 250 A VGS = 10 V, ID = 1.5 A VGS = 4.5 V, ID = 1.5 A 1.5 0.10 0.130 0.12 0.160 Min. 60 1 10 100 Typ. Max. Unit V A A nA V 2/9 STS3DPF60L ELECTRICAL CHARACTERISTICS (CONTINUED) Table 6: Dynamic Symbol gfs (*) Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDS = 10 V, ID = 3 A VDS = 25V f = 1 MHz VGS = 0 Min. Typ. 7.2 630 121 49 124 54 39 14.5 11.6 4.5 4.7 Max. Unit S pF pF pF ns ns ns ns Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd VDD = 30 V , ID = 1.5 A RG = 4.7 , VGS = 4.5 V (see Figure 16) VDD= 48V, ID= 3A VGS=4.5V (see Figure 19) 15.7 nC nC nC Table 7: Source Drain Diode Symbol ISD ISDM (*) VSD (*) trr Qrr IRRM (*) Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Test Conditions Min. Typ. Max. 3 12 Unit A A V ns nC A ISD = 3 A, VGS = 0 ISD = 3 A, di/dt = 100A/s VDD = 30 V, Tj = 150C (see Figure 17) 44 68.2 3.1 1.2 (*)Pulse width limited by safe operating area. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 3/9 STS3DPF60L Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/9 STS3DPF60L Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature Figure 11: Dource-Drain Diode Forward Characteristics Figure 14: Normalized Breakdown Voltage vs Temperature 5/9 STS3DPF60L Figure 15: Unclamped Inductive Load Test Circuit Figure 18: Unclamped Inductive Wafeform Figure 16: Switching Times Test Circuit For Resistive Load Figure 19: Gate Charge Test Circuit Figure 17: Test Circuit For Inductive Load Switching and Diode Recovery Times 6/9 STS3DPF60L SO-8 MECHANICAL DATA DIM. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm. MIN. TYP MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019 7/9 STS3DPF60L Table 8: Revision History Date 16-Sep-2004 Revision 1 New release. Description of Changes 8/9 STS3DPF60L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 9/9 |
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